FIG. 1 schematically shows a typical circuit of a 2-to-1 line decoder for a dynamic semiconductor memory device in the prior art. P-channel MOS transistors P1204 and P3206 together with N-channel MOS transistors N1208 and N3210 are transfer devices that connect a bit line pair BIT 200 and /BIT 201 to a sense amplifier and write circuit blocks. P-channel MOS transistors P2205 and P4207 and N-channel MOS transistors N2209 and N4211 likewise connect BIT2202 and /BIT2203 to the same ports of the sense amplifier and write blocks. To selectively transfer the column bit line pairs BIT 200 and /BIT 201 or BIT2202 and /BIT2203 to the sense amplifier for either a read or write operation, it is necessary to activate four separate control lines for reading and writing, namely, WY0216, WY1217, RY0214 and RY1215. In the interest of conserving chip real estate and performance it is as usual always desirable to provide a simplified bit line decoder with improved efficiency for either a read or a write operation.